In computing systems, memory latency or memory access time is the time between initiating a request for data until the requested data is retrieved from a memory. Memory can be tested to determine its memory access time. For example, the memory access time for a given memory indicates how fast that memory can provide data, which can allow more aggressive timings in the computing system. Also, the memory can be tested by comparing the determined memory access time with a threshold memory access time to determine whether the given memory “passes” or “fails”. As will be appreciated, if timings in the computing system are set too aggressively (e.g., due to an incorrect estimation of the memory's memory access time), memory errors can occur because the memory may not be capable of providing data fast enough for other system elements.
FIG. 1 illustrates a conventional memory test configuration for testing a memory access time of a memory. As shown in FIG. 1, the conventional memory test configuration includes an input register (IREG), a memory 105 (e.g., a random access memory (RAM), a read-only memory (ROM), etc.) and an output register (OREG) 110. While illustrated as separate elements, the IREQ 100, memory 105 and OREG 110 may collectively comprise a memory module that may be encapsulated within a wrapper.
Referring to FIG. 1, the IREG 100, memory 105 and OREG 110 are each connected to an input bus. As shown, the IREG 100 receives memory command information (e.g., an address location Addr, information for a write command, information for a read command, etc.) from the input bus. The IREG receives an input register clock signal ICLK, the memory 105 receives a memory clock signal MCLK and the OREG 110 receives the output register clock signal OCLK.
In an example, assume the memory command information on the input bus corresponds to a write command. The IREG 100 latches the write command information (e.g., write address, etc.) at a rising edge of ICLK after a setup time of the IREG 100. This information reaches input register output after a clock to queue delay.
Next, after a setup time of the memory 105, a rising edge of MLCK initiates the write command at the memory 105 based on the latched write command information from the IREG 100. Likewise, if the memory command information on the input bus corresponds to a read command, the IREG 100 latches the read command information at a rising edge of ICLK after a setup time of the IREG 100. Then, after a setup time of the memory 105, a rising edge of MLCK initiates the read command at the memory 105 based on the latched read command information from the IREG 100.
As will be appreciated, for a read operation, the timing of OCLK is configured such that a rising edge of OCLK corresponds to a time as close as possible after the memory 105 completes the read operation. In other words, OCLK should be more or less offset from MCLK by the memory access time. Accordingly, the OREG 110 latches the read data at a rising edge of OCLK after a setup time of the OREG 110. The latched read data can be read out through an output bus to output pins, as shown in FIG. 1. As will be appreciated, if OCLK is offset from MLCK less than the memory access time, incorrect data will be latched by the OREG 110.
Conventionally, in order to determine the memory access time for the memory 105, OCLK is initially offset from MCLK by a relatively high amount. Next, OCLK is adjusted and is moved closer to MCLK, in increments, until memory errors begin occurring. The occurrence of memory errors in this case are indicative of the OREG 110 latching incorrect data due to OCLK being too close to MCLK because the offset between OCLK and MCLK is less than the memory access time of the memory 105. Based on this process, the memory access time can be determined as follows:tACCESS—MEM=tpad—MCLK—OCLK(min)+tMCLK—OCLK—skew−tWIRE—delay−tSETUP—OREG  (1)wherein tACCESS—MEM denotes the calculated memory access time of the memory 105, tpad—MCLK—OCLK(min) denotes a measured minimum offset between MCLK and OCLK at which memory errors do not occur, tMCLK—OCLK—skew denotes a simulated skew between MCLK and OCLK, tWIRE—delay denotes a simulated wire propagation delay, tSETUP—OREG denotes a simulated setup time of the OREG 110.
In Equation 1, the simulated parameters tWIRE—delay, tSETUP—OREG and tMCLK—OCLK—skew generally occur due to either parasitic extraction or a timing closure tool (e.g., PRIMETIME) result. The simulated parameters tWIRE—delay, tSETUP—OREG and tMCLK—OCLK—skew reduce the precision of the determination of the memory access time tACCESS—MEM.